1. Field of the Invention
The invention relates to the field of semiconductor testing and packaging and more particularly to integrated circuit bond pad exposure, packaging, and testing.
2. Description of Related Art
In the manufacture of semiconductor devices, it is advisable that such devices be tested at the wafer level to evaluate their functionality. The process in which devices in a wafer are tested is commonly referred to as "wafer sort." Testing and determining design flaws at the wafer level offers several advantages. First, it allows designers to evaluate the functionality of new devices during development. Increasing packaging costs also make wafer sorting a viable cost saver, in that reliability of each device on a wafer may be tested before incurring the higher costs of packaging. Measuring reliability also allows the performance of the production process to be evaluated and production consistency rated, such as for example by "bin switching" whereby the performance of a device is downgraded because that device's performance did not meet the expected criteria.
FIG. 1 illustrates a surface view of the top side of an integrated circuit device. Metal interconnect lines and components of integrated circuit device 11 are formed on an underlying silicon substrate. The side of the silicon substrate on which the integrated circuit is formed shall herein be referred to as the top side of the silicon substrate. As illustrated in FIG. 1, bond pads 13 are located along the periphery of integrated circuit device 11. In the center of integrated circuit device 11 is the active region 12 containing the majority of the high density, active circuitry of integrated circuit device 11. To activate the circuitry within active region 12, it is necessary to supply voltage signals to bond pads 13. These voltage signals are supplied to bond pads 13 through a package to which integrated circuit device 11 is affixed.
FIG. 2 illustrates a cross-section of integrated circuit device 11 after packaging. After integrated circuit device 11 is affixed to package substrate 15, individual bond wires 14 are used to electrically couple each bond pad 13 to a corresponding pad on package substrate 15. Each corresponding pad 13 on package substrate 15 is then individually coupled to an external pin 16. The packaged integrated circuit device of FIG. 2 may then be placed within a socket in order to electrically couple external pin 16 to drivers that supply the necessary voltage signal to activate integrated circuit device 11. As illustrated in FIG. 2, integrated circuit device 11 is mounted to package substrate 15 with its top-side facing away from package substrate 15. In this manner, once integrated circuit device 11 is activated through package pin 16, the internal, active region 12 may be accessed and probed for testing since neither bond pads 13, package substrate 15, nor bond wires 14 obscure access to this region of integrated circuit device 11.
FIG. 3 illustrates a top-side view of a second bond pad configuration on an integrated circuit device. As illustrated in FIG. 3, bond pads 21 of integrated circuit device 20 are formed along the top of the entire integrated circuit device so that the bond pads now reside directly over the active circuitry region of integrated circuit device 20. By forming bond pads in both the center and periphery of integrated circuit device 20, more bond pads can be placed across the surface of the device than can be placed only within the peripheral region. In addition, active circuitry which underlies bond pads 21 of integrated circuit device can be directly coupled to its nearest bond pad using relatively short interconnect lines. This minimizes the resistive, capacitive, and inductive effects associated with routing interconnect lines over long distances, improving speed performance.
FIG. 4 is an illustration of a cross-section of integrated circuit device 20 after mounting to a package substrate 22. In order to mount integrated circuit device 20 to package substrate 22, solder balls 24 are placed on each of bond pads 21 to electrically couple each bond pad 21 to its corresponding pad on package substrate 22. Each corresponding pad on package substrate 22 is, in turn, coupled to an external pin 23. Integrated circuit device 20 is mounted to package substrate 22 with its top-side facing towards the package substrate. In other words, in comparison to the method used to mount integrated circuit device 11 to its package substrate in FIG. 2, integrated circuit device 20 is "flipped." For this reason, the design of integrated circuit device 20 illustrated in FIG. 3 and its subsequent packaging method illustrated in FIG. 4 is referred to as flip-chip technology. The technology is also known as Controlled Collapsable Chip Connection (C4), named after the package mounting technique of using solder to replace bond wires.
As noted above, integrated circuit device 11 (as shown in FIG. 1) or integrated circuit device 20 (as shown in FIG. 3) are fabricated with other devices on a wafer or die. FIG. 5 schematically represents a wafer 25 having a plurality of integrated circuit devices, including devices 30 and 35. The individual devices 30 and 35 are separated from one another by scribe streets 37. Once individual devices 30 and 35 are fabricated and electrically tested, wafer 25 is cut or sawed along scribe streets 37 to separate the devices, e.g., individual microprocessors.
FIG. 6 is an expanded view of a portion of wafer 25 showing individual integrated circuit devices 30 and 35 separated by scribe street 37. Each integrated circuit device 30 and 35 includes bond pads 32 located around the periphery of the top surface of the respective integrated circuit devices. Each integrated circuit device 30 and 35 is surrounded by a guard ring 36. Guard rings 36 are generally formed of conductive material similar to bond pads 32, such as for example aluminum (Al), aluminum-copper (Al--Cu) alloy, or aluminum-copper-silicon (Al--Cu--Si) alloy. Guard rings 36 are placed on the outside of bond pads 32 and serve to protect integrated circuit devices 30 and 35.
As noted above, one purpose of scribe street 37 is to provide a sawing or cutting area to allow devices 30 and 35 to be separated. A second purpose of scribe street 37 is to provide an area to place test mechanisms to ascertain the viability and reliability of integrated circuit devices 30 and 35. FIG. 6 shows scribe street 39 having a plurality of electrical test pads (E-Test pads) that facilitate testing of bond pads 32 and 33 of integrated circuit devices 30 and 35, respectively. A third purpose of scribe street 37 is to provide a location for placing alignment landmarks, schematically illustrated in FIG. 6 by reference numeral 38. Alignment landmarks 38 are used by the fabrication tooling in placing and fabricating individual structures on devices 30 and 35.
FIG. 7 shows a schematic cross-sectional planar side view of integrated circuit devices 30 and 35 taken through line A--A of FIG. 6. FIG. 7 shows integrated circuit device 30 having bond pad 32 and guard ring 34, and integrated circuit device 35 having bond pad 33 and guard ring 36. Integrated circuit devices 30 and 35 are separated by scribe street 37. Scribe street 37 includes E-Test pad 39 for testing devices for integrated circuit 30 and/or 35.
FIG. 7 shows the top conductive (e.g., metal) line of the integrated circuit devices 30 and 35. In general, after the devices are fabricated, bond pads 32 and 33 and E-Test pad 39 lie beneath dielectric layers and must be exposed for testing and bonding to a suitable package. In a typical process, bond pads 32 and 33, guard rings 34 and 36, and E-Test pad 39 are covered by a hard passivation layer of, for example, silicon nitride (Si.sub.3 N.sub.4). This hard passivation layer is covered by a soft passivation layer of, for example, a photodefinable polyimide. Together, the hard and soft passivation layers protect the device from the ambient, for example, scratches, moisture, and impurities.
FIGS. 8-10 illustrate the prior art process for exposing bond pads 32 and 33 of integrated circuit devices 30 and 35, respectively, and E-Test pad 39. As shown in FIG. 8, overlying the metal structures of integrated circuit devices 30 and 35 is a conformally deposited hard passivation layer 40, such as for example, silicon nitride. Next, as shown in FIG. 9, soft passivation layer 45, such as for example a photodefinable polyimide, is deposited over hard passivation layer 40.
FIG. 10 illustrates the processing steps of exposing bond pads 32 and 33 of integrated circuit devices 30 and 35, respectively, and E-Test pad 39. As a first step, photodefinable polyimide layer 45 is exposed to a light source. Portions of photodefinable polyimide layer 45 above bond pads 32 and 33 and E-Test pad 39 are protected from light exposure. The remaining photodefinable polyimide layer 45 is exposed and developed. During development, the unexposed region of photodefinable polyimide layer 45 is dissolved, exposing silicon nitride hard passivation layer 40 in those areas. Next, the remaining polyimide material is cured at high temperature. The exposed silicon nitride hard passivation layer 40 is then etched to remove silicon nitride from areas above bond pads 32 and 33 and E-Test pad 39. A suitable etchant is, for example, a NF.sub.3 /He and SF.sub.6 /He etch chemistries.
As shown in FIG. 10, hard passivation layer 40 and soft passivation layer 45 remain in a portion of scribe street area 37 although E-Test pad 39, along with bond pads 32 and 33, is partially exposed. The passivation process is now complete and E-Test pad 39 may be used to test scribe line test structures. Bond pad 32 of integrated circuit device 30 and bond pad 33 of integrated circuit device 35 can also be tested at this time. Once the devices are tested, passing devices are cut from the wafer and placed in a package. FIG. 11 illustrates the sawing process wherein the wafer is sawed through scribe street 37 to separate integrated circuit device 30 from integrated circuit device 35.
Once the integrated circuit devices are separated and placed in a package, the devices undergo a series of tests to evaluate their performance and their survival in the field. Various tests are done including, but not limited to, thermal cycling, moisture tests, impurity penetration, and reliability tests.
An integrated circuit device may be placed in a variety of packages. Common packages include ceramic, plastic, and other organic material packages. With regard to thermal cycling, plastic packages present a concern in that plastic and other organic material packages have a different thermal coefficient of expansion than a silicon-based device or chip. A typical thermal cycling test fluctuates the temperature to which a packaged device is exposed between approximately -80.degree. C. and 150.degree. C. Plastic and silicon do not expand and contract at the same rate when exposed to these temperature changes. The thermal coefficient of expansion of silicon is approximately three parts per million (ppm) while the thermal coefficient of expansion of a plastic substrate is approximately 20-25 ppm. Ceramic packages, on the other hand, have coefficients of thermal expansion very similar to silicon and do not show significant stresses due to the different materials. Thus, plastic and other organic material packages expand and contract much faster than their silicon-based contents which results in a great deal of stress between the package and the device or chip during thermal cycling. Nevertheless, plastic packages are preferred for other beneficial reasons, including cost and speed.
The stresses caused by thermal cycling result in particular failure areas in integrated circuit devices. One area of particular concern is the hard and soft passivation layers that overlie the integrated circuit devices, particularly in the area of the scribe street. It has been observed that during the thermal cycling process, the passivation layers experience a lifting or delamination of hard and soft passivation layer material. This is illustrated by reference numeral 42 in FIG. 11. It is believed that the delamination occurs because the interface between, for example, a silicon nitride hard passivation layer 40 and a polyimide soft passivation layer 45 is very weak.
Delamination between soft passivation layer 45 and hard passivation layer 40 is also seen during the saw process where individual devices are separated. The saw cutting process incurs damage to the passivation resulting in delamination at the interface between soft passivation layer 45 and hard passivation layer 40. In addition, during sawing, thin strips get separated from soft passivation layer 45 and form what are known as "stringers" 43, commonly polyimide stringers 43, that can get redeposited on top of the bond pads. Further, during sawing through E-test pad 39, thin strips of metal along with hard and soft passivation layer material get separated from the scribe street and form what are known as "lifted-edge metal" that can be redeposited on top of the bond pads. These metal stringers interfere with further processing and cause shorting between bond pads 32 and 33 and cause yield loss. Thus, the presence of stringers and lifted-edge metal on the metal pads interferes with and inhibits further processing and testing and results in yield loss.
Delamination 42 minimizes the integrity of the device, because the separated soft passivation layer 45 no longer serves as a protectant to the generally brittle hard passivation layer 40. Delamination also affects the integrity of the integrated circuit device by producing stringers that interfere with further processing and testing. These negative influences on integrated circuit device integrity causes the device to lose its robustness. A loss of robustness is equivalent to a yield loss as the integrated circuit device is no longer suitable for a prescribed use.